DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 32

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex)
12.0 LINE INTERFACE FUNCTIONS
The line interface function in the DS2151Q contains three sections; (1) the receiver which handles clock
and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter
attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR),
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex)
(MSB)
(MSB)
CH16
CH24
CH8
L2
CH15
CH23
CH7
L1
SYMBOL POSITION NAME AND DESCRIPTION
SYMBOL POSITION NAME AND DESCRIPTION
JABDS
CH24
EGL
DJA
CH1
JAS
CH14
CH22
CH6
L2
L1
L0
L0
RMR3.7
RMR1.0
LICR.7
LICR.6
LICR.5
LICR.4
LICR.3
LICR.2
LICR.1
CH13
CH21
CH5
EGL
Line Build Out Select Bit 2. Sets the transmitter build
out; see the Table 12-2
Line Build Out Select Bit 1. Sets the transmitter build
out; see the Table 12-2
Line Build Out Select Bit 0. Sets the transmitter build
out; see the Table 12-2
Receive Equalizer Gain Limit.
0= -36 dB
1= -30 dB
Jitter Attenuator Select.
0=place the jitter attenuator on the receive side
1=place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0=128 bits
1=32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0=jitter attenuator enabled
Receive Channel Blocking Registers.
0=do not affect the receive data associated with this
channel
1=replace the receive data associated with this channel
with either the idle code or the digital milliwatt code
(depends on the RCR2.7 bit)
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CH12
CH20
CH4
JAS
CH11
CH19
JABDS
CH3
CH10
CH18
CH2
DJA
(LSB)
CH17
CH1
CH9
(LSB)
TPD
RMR1 (2D)
RMR2 (2E)
RMR3 (2F)
LICR
DS2151Q