DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 34

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

LBO SELECT IN LICR Table 12-2
Due to the nature of the design of the transmitter in the DS2151Q, very little jitter (less then 0.005 UIpp
broad-band from 10 Hz to 100 kHz) is added to the jitter present on TCLK. Also, the waveforms that
they create are independent of the duty cycle of TCLK. The transmitter in the DS2151Q couples to the
T1 transmit twisted pair via a 1:1.15 or 1:1.36 step up transformer as shown in Figure 12-1. In order for
the devices to create the proper waveforms, the transformer used must meet the specifications listed in
Table 12-3.
TRANSFORMER SPECIFICATIONS Table 12-3
12.3 JITTER ATTENUATOR
The DS2151Q contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 12-4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA-bit in the LICR. In
order for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 12-4
below must be connected to the XTAL1 and XTAL2 pins. The jitter attenuator divides the clock
provided by the 6.176 MHz crystal at the XTAL1 and XTAL2 pins to create an output clock that contains
very little jitter. Onboard circuitry will pull the crystal (by switching in or out load capacitance) to keep it
long-term averaged to the same frequency as the incoming T1 signal. If the incoming jitter exceeds either
120UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS2151Q will divide the
attached crystal by either 3.5 or 4.5 instead of the normal 4 to keep the buffer from overflowing. When
the device divides by either 3.5 or 4.5, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the
Receive Information Register 2 (RIR2.2).
Turns Ratio
Primary Inductance
Leakage Inductance
Intertwining Capacitance
DC Resistance
L2
0
0
0
0
1
1
1
1
SPECIFICATION
L1
0
0
1
1
0
0
1
1
L0
0
1
0
1
0
1
0
1
34 of 51
LINE BUILD OUT
0 to 133 feet/0 dB
133 to 266 feet
266 to 399 feet
399 to 533 feet
533 to 655 feet
1:1 (receive) and 1:1.15 or 1:1.36 (transmit) 5%
600 H minimum
1.0 H maximum
40 pF maximum
1.2 ohms maximum
-22.5 dB
-7.5 dB
-15 dB
RECOMMENDED VALUE
APPLICATION
DSX-1/CSU
DSX-1
DSX-1
DSX-1
DSX-1
CSU
CSU
CSU
DS2151Q