DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 25

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

6.0 FDL/FS EXTRACTION AND INSERTION
The DS2151Q has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs bit position in the D4 framing mode. Since SLC-96 utilizes the Fs bit
position, this capability can also be used in SLC-96 applications. The operation of the receive and
transmit sections will be discussed separately.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
DS2151Q will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled
via IMR2.4, the
user has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes
programmed into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the
pin will be toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore
the FDL or Fs pattern until an important event occurs.
The DS2151Q also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than five 1s should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2151Q
will automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will
automatically remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not
removed. The CCR2.0 bit should always be set to a 1 when the DS2151Q is extracting the FDL. More
on how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate Application Note.
Also, contact the factory for C code software that implements both ANSI T1.403 and AT&T
TR54016.
RFDL: RECEIVE FDL REGISTER (Address=28 Hex)
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address=29 Hex)
RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address=2A Hex)
RFDL7
RFDL7
(MSB)
(MSB)
RFDL6
RFDL6
INT2
SYMBOL POSITION NAME AND DESCRIPTION
SYMBOL POSITION NAME AND DESCRIPTION
RFDL7
RFDL0
RFDL7
RFDL0
pin will toggle low indicating that the buffer has filled and needs to be read. The
RFDL5
RFDL5
RFDL.7
RFDL.0
RFDL.7
RFDL.0
RFDL4
RFDL4
MSB of the FDL Match Code
LSB of the FDL Match Code
MSB of the Received FDL Code
LSB of the Received FDL Code
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RFDL3
RFDL3
RFDL2
RFDL2
RFDL1
RFDL1
RFDL0
RFDL0
(LSB)
(LSB)
DS2151Q
INT2