PEB3265 Infineon Technologies Corporation, PEB3265 Datasheet - Page 139

• Manufacturer Part Number: PEB3265
• Description: (PEB326x / PEB426x) Dual Channel Slicofi-2 / Slic Duslic
• Manufacturer: Infineon Technologies Corporation

Preliminary
clock rate is twice the data rate), the first rising edge indicates the start of a bit, while, by
default, the second falling edge is used to buffer the contents of the data line DRA (DRB).
Figure 58
The data rate of the interface can vary from 2*128 kbit/s to 2*8192 kbit/s (two highways).
A frame may consist of up to 128 time slots of 8 bits each. The time slot and PCM
Data Sheet
FSC
DRA
DXA
TCA
PCLK
DETAIL A:
Time Slot
General PCM Interface Timing
0 1 2
FSC
DRA
DXA
TCA
PCLK
Detail A
3
High 'Z'
Clock
Bit
High 'Z'
7
0 1
6
5
2 3 4 5 6
139
Voice
Voice
Data
Data
4
3
2
125 µs
1
0
7
High 'Z'
High 'Z'
Time Slot
ezm14046.wmf
31
Interfaces
2000-07-14
DuSLIC