PEB3265 Infineon Technologies Corporation, PEB3265 Datasheet - Page 92

• Manufacturer Part Number: PEB3265
• Description: (PEB326x / PEB426x) Dual Channel Slicofi-2 / Slic Duslic
• Manufacturer: Infineon Technologies Corporation

Preliminary
4.6
SLICOFI-2x provides much interrupt data for the host system. Interrupt handling is
performed by the on chip microprogram which handles the interrupts in a fixed 2 kHz
(500 s) frame. Therefore, some delays up to 500 s can occur in the reactions of
SLICOFI-2x depending on when the host reads the interrupt registers.
Independent of the selected interface mode (PCM/ C or IOM-2), the general behavior of
the interrupt is as follows:
• Any change (at some bits only transitions from 0 to 1) in one of the four interrupt
• In IOM-2 interface mode, the interrupt channel bits are fed to the CIDU channel (see
• The interrupt is released (INT-CH bit reset to zero) by reading all four interrupt
• A hardware or power-on reset of the chip clears all pending interrupts and resets the
Data Sheet
registers leads to an interrupt. The interrupt channel bit INT-CH in INTREG1 is set to
one and all interrupt registers of one DuSLIC channel are locked at the end of the
interrupt procedure (500 µs period). Therefore all changes within one 2 kHz frame are
stored in the interrupt registers. The lock remains until the interrupt channel bit is
cleared (Release Interrupt by reading all four interrupt registers INTREG1 to
INTREG4 with one command).
IOM-CIDU). In PCM mode, the INT pin is set to active (low).
registers by one command. Reading the interrupt registers one by one using a series
of commands does not release the interrupt even if all four registers are read.
INT line to inactive (PCM/µC mode) or resets the INT-CH bit in CIDU (IOM-2 mode).
The behavior after a software reset of both channels is similar, the interrupt signal
switches to non-active within 500 s. A software reset of one DuSLIC channel
deactivates the interrupt signal if there is no active interrupt on the other DuSLIC
channel.
If the reset line is deactivated, a reset interrupt is generated for each channel (bit
RSTAT in register INTREG2).
Interrupt Handling
92
Operational Description
2000-07-14
DuSLIC