PEB3265 Infineon Technologies Corporation, PEB3265 Datasheet - Page 88

• Manufacturer Part Number: PEB3265
• Description: (PEB326x / PEB426x) Dual Channel Slicofi-2 / Slic Duslic
• Manufacturer: Infineon Technologies Corporation

Preliminary
4.5
4.5.1
A reset of the DuSLIC is initiated by a power-on reset or a hardware reset by setting the
signal at RESET input pin to low level for at least 4 µs
rejection which will safely suppress spikes with an duration of less than 1 µs
By setting the reset signal to low, the chip will be reset (see
• all I/O pins deactivated
• all outputs inactive (e.g. DXA/DXB)
• internal PLL stopped
• internal clocks deactivated
• chip in power down high impedance (PDH)
With the high going reset signal, the following actions take place:
• Clock detection
• PLL synchronization
• Running the reset routine
The internal reset routine will then initialize the whole chip to default condition as
described in the SOP default register setting (see
reset routine it is necessary that all external clocks are supplied:
• µC/PCM mode: FSC, MCLK, PCLK
• IOM-2 mode: FSC and DCL.
Without valid and stable external clock signals, the DuSLIC will not finish the reset
sequence properly.
The internal reset routine requires 12 frames (125 µs) to be finished (including PLL start
up and clock synchronization) and is setting the default values given in
first register access to the SLICOFI-2x may be done after the internal reset routine is
finished.
1)
2)
Data Sheet
Maximum spike rejection time t
Minimum spike rejection time t
Reset Mode and Reset Behavior
Hardware and Power On Reset
rej,min
rej, max
88
Chapter
1)
. The reset input pin has a spike
6). To run through the internal
Figure
Operational Description
39):
Table
2)
2000-07-14
.
DuSLIC
16. The