PEB3265 Infineon Technologies Corporation, PEB3265 Datasheet - Page 177

• Manufacturer Part Number: PEB3265
• Description: (PEB326x / PEB426x) Dual Channel Slicofi-2 / Slic Duslic
• Manufacturer: Infineon Technologies Corporation

Preliminary
Bit
After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the
default value of INTREG2 is 20h. After reading all four interrupt registers, the INTREG2
value changes to 4Fh.
LM-THRES
READY
RSTAT
LM-OK
IO[4:1]-DU
Data Sheet
08
H
INTREG2
THRES
LM-
7
Data on IO pins 1 to 4 filtered by DUP-IO counter and interrupt generation
masked by the IO[4:1]-DU-M bits. A change of any of this bits generates
an interrupt.
Reset status since last interrupt.
RSTAT = 0
RSTAT = 1
Level metering sequence has finished. An interrupt is only generated if
the LM-OK bit changes from 0 to 1.
LM-OK = 0
LM-OK = 1
Indication whether the level metering result is above or below the
threshold set by the CRAM coefficients
LM-THRES = 0 Level metering result is below threshold.
LM-THRES = 1 Level metering result is above threshold.
Indication whether the ramp generator has finished. An interrupt is only
generated if the READY bit changes from 0 to 1. Upon a new start of the
ramp generator, the bit is set to 0. For further information regarding soft
reversal see
READY = 0
READY = 1
READY RSTAT
6
Interrupt Register 2 (read-only)
Chapter
Ramp generator active.
Ramp generator not active.
No reset has occurred since the last interrupt.
Reset has occurred since the last interrupt.
Level metering result not ready.
Level metering result ready.
5
SLICOFI-2x Command Structure and Programming
3.7.2.1.
LM-OK
4
177
3
2
IO[4:1]-DU
20
DuSLIC-E/-E2/-P
H
1
2000-07-14
0
Y