PEB3265 Infineon Technologies Corporation, PEB3265 Datasheet - Page 173

• Manufacturer Part Number: PEB3265
• Description: (PEB326x / PEB426x) Dual Channel Slicofi-2 / Slic Duslic
• Manufacturer: Infineon Technologies Corporation

Preliminary
Bit
DBL-CLK
X-SLOPE
R-SLOPE
NO-
DRIVE-0
SHIFT
PCMO[2:0] The whole PCM timing is moved by PCMO data periods against the FSC
Data Sheet
05
H
DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0
PCMC1
7
Clock mode for the PCM interface (see
DBL-CLK = 0
DBL-CLK = 1
Transmit slope (see
X-SLOPE = 0
X-SLOPE = 1
Receive slope (see
R-SLOPE = 0
R-SLOPE = 1
Driving mode for bit 0 (only available in single-clocking mode).
NO-DRIVE = 0
NO-DRIVE = 1
Shifts the access edges by one clock cycle in double-clocking mode.
SHIFT = 0
SHIFT = 1
signal.
PCMO[2:0] = 0 0 0
PCMO[2:0] = 0 0 1
PCMO[2:0] = 1 1 1
6
PCM Configuration Register 1
SLICOFI-2x Command Structure and Programming
5
Figure 59
Figure 59
Transmission starts with rising edge of the clock.
Transmission starts with falling edge of the clock.
Single-clocking is used.
Double-clocking is used.
Data is sampled with falling edge of the clock.
Data is sampled with rising edge of the clock.
No shift takes place.
Shift takes place.
Bit 0 is driven the entire clock period.
Bit 0 is driven during the first half of the clock period
only.
No offset is added.
One data period is added.
Seven data periods are added.
173
on
on
4
Page
Page
Figure 59
141)
141)
SHIFT
3
on
00
Page
DuSLIC-E/-E2/-P
2
H
PCMO[2:0]
141)
1
2000-07-14
N
0