S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 269

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Read: Anytime.
Write: Only if a transition is allowed (see
The MODC bit of the MODE register is used to select the MCU’s operating mode.
5.3.2.2
Read: Anytime
Write: anytime in special SS, write-once in NS.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both
global and local mapping scheme.
Freescale Semiconductor
Address: 0x0011
Reset
MODC
Field
7
W
R
DP15
Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external
mode pin MODC determines the operating mode during RESET low (active). The state of the pin is registered
into the respective register bit after the RESET signal goes inactive (see
Write restrictions exist to disallow transitions between certain modes.
changes. Attempting non authorized transitions will not change the MODE bit, but it will block further writes to
the register bit except in special modes.
Write accesses to the MODE register are blocked when the device is secured.
Direct Page Register (DIRECT)
0
7
Figure 5-4. Mode Transition Diagram when MCU is Unsecured
DP14
0
6
Single-Chip
Normal
(NS)
1
MC9S12G Family Reference Manual, Rev.1.23
Figure 5-5. Direct Register (DIRECT)
Table 5-4. MODE Field Descriptions
DP13
0
5
Figure
1
DP12
RESET
5-4).
0
4
1
Description
0
DP11
0
3
Single-Chip
S12G Memory Map Controller (S12GMMCV1)
Special
Figure 5-4
(SS)
DP10
0
Figure
0
2
5-4).
illustrates all allowed mode
DP9
0
1
DP8
0
0
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