S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 372

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.2
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
374
0x0035
Reset
If XOSCLCP is enabled (OSCE=1)
If XOSCLCP is disabled (OSCE=0)
W
R
S12CPMU Reference Divider Register (CPMUREFDIV)
0
7
REFFRQ[1:0]
Write to this register clears the LOCK and UPOSC status bits.
Table 10-2. Reference Clock Frequency Selection if OSC_LCP is enabled
Figure 10-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Table
0
6
10-2.
REFCLK Frequency Ranges
MC9S12G Family Reference Manual,
1MHz <= f
6MHz < f
2MHz < f
0
0
5
f
REF
(OSCE=1)
REF
f REF
f REF
REF
>12MHz
REF
<= 12MHz
<= 6MHz
<= 2MHz
=
=
NOTE
------------------------------------
(
f IRC1M
0
0
4
REFDIV
f OSC
+
1
)
1
3
REFFRQ[1:0]
Rev.1.23
00
01
10
11
1
2
REFDIV[3:0]
Freescale Semiconductor
1
1
REF
1
0
<=