S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 510

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Analog-to-Digital Converter (ADC12B12CV2)
14.3.2.7
This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and
the conversion counter.
Read: Anytime
Write: Anytime (No effect on (CC3, CC2, CC1, CC0))
512
Module Base + 0x0006
ETORF
Reset
FIFOR
Field
SCF
7
5
4
W
R
SCF
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared
when one of the following occurs:
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
0 No External trigger overrun error has occurred
1 External trigger overrun error has occurred
Result Register Overrun Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read
(i.e. the old data has been lost). This flag is cleared when one of the following occurs:
0 No overrun has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag was still set)
ATD Status Register 0 (ATDSTAT0)
0
7
A) Write “1” to ETORF
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
A) Write “1” to FIFOR
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and a result register is read
= Unimplemented or Reserved
0
0
6
Figure 14-9. ATD Status Register 0 (ATDSTAT0)
Table 14-16. ATDSTAT0 Field Descriptions
MC9S12G Family Reference Manual,
ETORF
0
5
FIFOR
0
4
Description
CC3
0
3
Rev.1.23
CC2
0
2
Freescale Semiconductor
CC1
0
1
CC0
0
0