S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 362

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.1.2
This subsection lists and briefly describes all operating modes supported by the S12CPMU.
10.1.2.1
The voltage regulator is in Full Performance Mode (FPM).
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
10.1.2.2
For S12CPMU Wait Mode is the same as Run Mode.
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PLL Engaged Internal (PEI)
— This is the default mode after System Reset and Power-On Reset.
— The Bus Clock is based on the PLLCLK.
— After reset the PLL is configured for 50 MHz VCOCLK operation
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
PLL Engaged External (PEE)
— The Bus Clock is based n the PLLCLK.
— This mode can be entered from default mode PEI by performing the following steps:
PLL Bypassed External (PBE)
— The Bus Clock is based on the Oscillator Clock (OSCCLK).
— The PLLCLK is always on to qualify the external oscillator clock. Therefore it is necessary to
— This mode can be entered from default mode PEI by performing the following steps:
— The PLLCLK is on and used to qualify the external oscillator clock.
Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is
6.25MHz.
The PLL can be re-configured for other bus frequencies.
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1).
make sure a valid PLL configuration is used for the selected oscillator frequency.
– Make sure the PLL configuration is valid for the selected oscillator frequency.
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1)
– Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0).
Modes of Operation
Run Mode
Wait Mode
necessary.
MC9S12G Family Reference Manual,
Rev.1.23
Freescale Semiconductor