S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 481

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

13.3.2.6
Writes to this register will abort current conversion sequence and start a new conversion sequence. If the
external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting
of a conversion sequence which will then occur on each trigger event. Start of conversion means the
beginning of the sampling phase.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0005
CD, CC,
CB, CA
Reset
SCAN
MULT
Field
3–0
SC
6
5
4
W
R
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,
CC, CB and CA of ATDCTL5.
0 Special channel conversions disabled
1 Special channel conversions enabled
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect,
thus the external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0).
0 Sample only one channel
1 Sample across several channels
Analog Input Channel Select Code — These bits select the analog input channel(s).
coding used to select the various analog input channels.
In the case of single channel conversions (MULT=0), this selection code specifies the channel to be examined.
In the case of multiple channel conversions (MULT=1), this selection code specifies the first channel to be
examined in the conversion sequence. Subsequent channels are determined by incrementing the channel
selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel
Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by
WRAP3-0 the first wrap around will be AN11 to AN0.
ATD Control Register 5 (ATDCTL5)
0
0
7
= Unimplemented or Reserved
SC
0
6
Figure 13-8. ATD Control Register 5 (ATDCTL5)
Table 13-14. ATDCTL5 Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
SCAN
Table 13-15
0
5
lists the coding.
MULT
0
4
Description
CD
0
3
Analog-to-Digital Converter (ADC10B12CV2)
CC
0
2
Table 13-15
CB
0
1
lists the
CA
0
0
483