S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 594

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Freescale’s Scalable Controller Area Network (S12MSCANV3)
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
18.3.2.5
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
596
Module Base + 0x0004
Reset:
W
R
1
MSCAN Receiver Flag Register (CANRFLG)
WUPIF
This setting is not valid. Please refer to
TSEG13
Bit Time
1
0
7
This setting is not valid. Please refer to
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
Figure 18-8. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
CSCIF
=
6
0
TSEG12
(
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
MC9S12G Family Reference Manual,
f CANCLK
TSEG21
Table 18-10. Time Segment 1 Values
Table 18-9. Time Segment 2 Values
RSTAT1
0
0
1
1
:
0
5
TSEG11
0
0
1
1
1
1
:
Table 18-9
Table 18-37
TSEG20
RSTAT0
)
•
Table 18-37
4
0
0
1
0
1
:
(
1
TSEG10
+
and
TimeSegment1
0
1
0
1
0
1
:
for valid settings.
TSTAT1
Table
for valid settings.
0
3
Rev.1.23
Time Segment 2
1 Tq clock cycle
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
18-10).
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
1 Tq clock cycle
4 Tq clock cycles
TSTAT0
:
2
0
+
TimeSegment2
:
1
Access: User read/write
Freescale Semiconductor
1
OVRIF
1
1
0
1
)
Eqn. 18-1
RXF
0
0
1