DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 17

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

Chapter 4: Development Board Setup
Factory Default Switch Settings
Table 4–2. SW4 Dip Switch Settings
Table 4–3. JTAG Chain Jumper Settings (Part 1 of 2)
July 2010 Altera Corporation
1
2
3
4
5
6
7
8
J9 pins 1-2
J9 pins 3-4
Switch
Reference
Board
DIP0
DIP1
DIP2
USR LOAD
PWR MON
USB DISn
CLK EN
CLK SEL
MAX DIS
HSMA DIS
Board
Label
Board
Label
2. Set DIP switch bank (SW4) to match
3. Set the board jumpers to match
Switch 1 has the following options:
■
■
Switch 2 has the following options:
■
■
Switch 3 has the following options:
■
■
Switch 4 has the following options:
■
■
Switch 5 has the following options:
■
■
Switch 6 has the following options:
■
■
Switch 7 has the following options:
■
■
Switch 8 has the following options:
■
■
When on, reserved.
When off, reserved.
When on, reserved.
When off, reserved.
When on, reserved.
When off, reserved.
When on, the PFL loads the user hardware 1 design on power up.
When off, the PFL loads the factory design on power up.
When on, reserved.
When off, reserved.
When on, reserved.
When off, reserved.
When on, all on-board oscillators are enabled.
When off, on-board oscillators to the FPGA are disabled.
When on, programmable oscillator clock (U30) is selected.
When off, LVPECL SMA clock (J10 and J11) is selected.
This jumper has the following options:
■
■
This jumper has the following options:
■
■
Installing the shunt removes the MAX II EPM2210 device from the
JTAG chain.
Removing the shunt includes the MAX II EPM2210 device in the
JTAG chain.
Installing the shunt removes HSMC port A from the JTAG chain.
Removing the shunt includes HSMC port A in the JTAG chain.
Table 4–3
Function
Function
Table 4–2
and
Arria II GX FPGA Development Kit, 6G Edition User Guide
Figure
and
Figure
4–1.
4–1.
Shunt Position
Not installed
Installed
Default
Position
Default
Off
Off
Off
Off
Off
Off
On
On
4–3