DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 45

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

Chapter :
Restoring the MAX II CPLD to the Factory Settings
Restoring the MAX II CPLD to the Factory Settings
July 2010 Altera Corporation
f
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12. Cycle the POWER switch (SW1) off then on to load and run the restored factory
13. The restore script cannot restore the board’s MAC address automatically. In the
To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
of the Altera website.
This section describes how to restore the original factory contents to the MAX II CPLD
on the FPGA development board, 6G edition. Make sure you have the Nios II EDS
installed, and perform the following instructions:
1. Set the board switches to the factory default settings described in
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select <install
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX II CPLD.
To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
of the Altera website.
design.
Nios II command shell, type the following Nios II EDS command:
nios2-terminal r
and follow the instructions in the terminal window to generate a unique MAC
address.
Switch Settings” on page
1
dir>\kits\arriaIIGX_2agx260_fpga\factory_recovery\max2.pof.
Configuration is complete when the progress bar reaches 100%.
Uninstalling the shunt jumper from jumper J9 pins 1-2 includes the MAX II
device in the JTAG chain.
4–2.
Arria II GX FPGA Development Kit, 6G Edition
Arria II GX FPGA Development Kit, 6G Edition
Arria II GX FPGA Development Kit, 6G Edition User Guide
“Factory Default
page
page
A–5