DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 34

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

6–14
Figure 6–7. The HSMC Tab
Arria II GX FPGA Development Kit, 6G Edition User Guide
The HSMC Tab
1
The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B
ports.
You must have the loopback HSMC installed on the HSMC connector that you are
testing for this test to work correctly.
The following sections describe the controls on the HSMC tab.
Status
The Status control displays the following status information during the loopback test:
■
■
■
PLL lock—Shows the PLL locked or unlocked state.
Channel lock—Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Figure 6–7
shows the HSMC tab.
Chapter 6: Board Test System
July 2010 Altera Corporation
Using the Board Test System