AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 11

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5. Blockdiagram
Figure 5-1.
32015G–AVR32–09/09
PC
PD
PA
PB
PE
XOUT32
D+
D-
XOUT0
XOUT1
XIN32
PLL0
XIN0
XIN1
PLL1
Blockdiagram
TRST_N
TCK
TDO
TMS
TDI
OSCEN_N
RESET_N
DATA[11..0]
HSYNC
VSYNC
PCLK
32 KHz
DATA[7..0]
OSC0
OSC1
PLL0
PLL1
OSC
CLK[2..0]
EVTI_N
NMI_N
CMD
MSEO[1..0]
MDO[5..0]
INTERFACE
INTERFACE
INTERFACE
EVTO_N
MCKO
INTRAM0
INTRAM1
SENSOR
IMAGE
JTAG
DMA
USB
AC97 CONTROLLER
MULTIMEDIA CARD
TIMER/COUNTER 0/1
AUDIO BITSTREAM
DMA CONTROLLER
CONTROLLER
CONTROLLER
CONTROLLER
CONTROLLER
GENERATOR
INTERFACE
INTERRUPT
MANAGER
EXTERNAL
POWER
CLOCK
CLOCK
SLEEP
RESET
DAC
PB
HSB-PB
BRIDGE
M
M
S
S
B
CLASS 3
NEXUS
HS
S
OCD
B
M
M
M
CONFIGURATION
S
MEMORY MANAGEMENT UNIT
HIGH SPEED
BUS MATRIX
BRIDGE A
CACHE
INSTR
HSB-PB
HSB
PB
M
S
REGISTERS BUS
AP CPU
HSB-HSB BRIDGE
CONTROLLER 0/1/2
PS2 INTERFACE
CONTROLLER
CONTROLLER
CONTROLLER
SYNCHRONOUS
PULSE WIDTH
MODULATION
CACHE
PERIPHERAL
INTERFACE 0/1
WATCHDOG
INTERFACE
INTERRUPT
DATA
PERIPHERAL
TWO-WIRE
REAL TIME
COUNTER
M
TIMER
USART0
USART1
USART2
USART3
SERIAL
SERIAL
DMA
M
S
TX_CLOCK, TX_FRAME_SYNC
RX_CLOCK, RX_FRAME_SYNC
PIXEL COPROCESSOR
MISO, MOSI
CLOCK[1..0]
NPCS[3..1]
DATA[1..0]
RTS, CTS
RX_DATA
TX_DATA
NPCS0
PWM0
PWM1
PWM2
PWM3
RXD
TXD
CLK
SCK
SCL
SDA
ADDR[23..25]
DATA[31..16]
NCS[5,4,2]
CFRNW,
CFCE1,
CFCE2,
NWAIT
AT32AP7001
ADDR[22..0]
DATA[15..0]
NCS[3,1,0],
NANDWE,
NANDOE,
SDCKE,
SDWE,
NWE3,
NWE1,
NWE0,
SDCK,
RAS,
CAS,
NRD,
PA
PB
PC
PD
PE
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