AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 47
AT32AP7001-ALUT
Manufacturer Part Number
AT32AP7001-ALUT
Description
IC MCU 32BIT AVR32 208-LQFP
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7001-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, POR, PWM, WDT
Number Of I /o
90
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, ISI, MCI, PS2, SPI, TWI, USB
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 1 Channel
Package
208PQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32AP7001-ALUT
Manufacturer:
EVERLIGHT
Quantity:
12 000
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8.7.1.16
Register Name: CONFIG
Access Type: Read/Write
• OIM: Output Insertion Mode
The OIM bit specifies the semantics of the OUTd output pixel address parameter to the pico(s)v(mul/mac) instructions. The
OIM together with the output pixel address parameter specify which of the 12 output bytes (OUTn) of the OUTPIXn regis-
ters will be updated with the results from the VMUs.
See
Table 8-2.
• ISM: Input Selection Mode
T h e I S M f i e l d s p e c i f i e s t h e s e m a n t i c s o f t h e i n p u t p i x e l a d d r e s s p a r a m e t e r s I N x , I N y a n d I N z t o t h e
pico(s)v(mul/mac) instructions. Together with the three input pixel addresses the ISM field specifies to the Input Pixel
Selector which of the input pixels (INn) that should be selected as inputs to the
32015G–AVR32–09/09
OIM
0
1
Section 8.6 ”Output Pixel Inserter” on page 29
31
23
15
7
-
-
-
Mode
Packed Insertion Mode
Planar Insertion Mode
PICO Configuration Register
Output Insertion Modes
OFFSET_FRAC_BITS
30
22
14
6
-
-
-
Description
{OUTPIX0, OUTPIX1, OUTPIX2} is treated as one large register containing 4 sequential 24-
bit pixel triplets. The DST_ADR field specifies which of the sequential triplets will be updated.
OUT(d*3 + 0) ← Scaled and saturated output from VMU0
OUT(d*3 + 1) ← Scaled and saturated output from VMU1
OUT(d*3 + 2) ← Scaled and saturated output from VMU2
Each of the OUTPIXn registers will get one of the resulting pixels. The triplet address
specifies what byte in each of the OUTPIXn registers the results will be written to.
OUT(d + 0) ← Scaled and saturated output from VMU0
OUT(d+ 4) ← Scaled and saturated output from VMU1
OUT(d + 8) ← Scaled and saturated output from VMU2
29
21
13
5
-
-
-
for a description of the Output Pixel Inserter.
28
20
12
Table 8-2 on page 47
4
-
-
-
27
19
11
3
-
-
-
describes the different Output Insertion Modes.
VMUs.Table 8-3 on page 48
OIM
COEFF_FRAC_BITS
26
18
10
2
-
-
AT32AP7001
25
17
9
1
-
-
ISM
describes the
24
16
8
0
-
-
47
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