AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 161

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

17.6
17.6.1
17.7
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
32015G–AVR32–09/09
Product Dependencies
Functional Description
I/O Lines
Bus Multiplexing
Pull-up Control
Static Memory Controller
SDRAM Controller
ECC Controller
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
The EBI transfers data between the internal HSB Bus (handled by the HMatrix) and the external
memories or peripheral devices. It controls the waveforms and the parameters of the external
address, data and control busses and is composed of the following elements:
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• The ECC Controller (ECC)
• A chip select assignment feature that assigns an HSB address space to the external devices
• A multiplex controller circuit that shares the pins between the different Memory Controllers
• Programmable CompactFlash support logic
• Programmable SmartMedia and NAND Flash support logic
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 26 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
A specific HMATRIX_SFR register in the Matrix User Interface permit enabling of on-chip pull-up
resistors on the data bus lines not multiplexed with the PIO Controller lines. For details on this
register, refer to the Peripherals Section. The pull-up resistors are enabled after reset. Setting
the EBI_DBPUC bit disables the pull-up resistors on lines not muxed with PIO. Enabling the pull-
up resistor on lines multiplexed with PIO lines can be performed by programming the appropri-
ate PIO controller.
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
For information on the SDRAM Controller, refer to the SDRAM Section.
For information on the ECC Controller, refer to the ECC Section.
AT32AP7001
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