AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 673

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Used for OUT transfers only.
0 = USB end of transfer is ignored.
1 = USBA device can put an end to the current buffer transfer.
When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close
the current buffer and the DMASTATUSx register END_TR_ST flag will be raised.
This is intended for USBA non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data
buffer closure.
• END_B_EN: End of Buffer Enable (Control)
0 = DMA Buffer End has no impact on USB packet transfer.
1 = endpoint can validate the packet (according to the values programmed in the EPTCTLx register AUTO_VALID and
SHRT_PCKT fields) at DMA Buffer End, i.e. when the DMASTATUS register BUFF_COUNT reaches 0.
This is mainly for short packet IN validation initiated by the DMA reaching end of buffer, but could be used for OUT packet
truncation (discarding of unwanted packet data) at the end of DMA buffer.
• END_TR_IT: End of Transfer Interrupt Enable
0 = USBA device initiated buffer transfer completion will not trigger any interrupt at STATUSx/END_TR_ST rising.
1 = an interrupt is sent after the buffer transfer is complete, if the USBA device has ended the buffer transfer.
Use when the receive size is unknown.
• END_BUFFIT: End of Buffer Interrupt Enable
0 = DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.
1 = an interrupt is generated when the DMASTATUSx register BUFF_COUNT reaches zero.
• DESC_LD_IT: Descriptor Loaded Interrupt Enable
0 = DMASTATUSx/DESC_LDST rising will not trigger any interrupt.
1 = an interrupt is generated when a descriptor has been loaded from the bus.
• BURST_LCK: Burst Lock Enable
0 = the DMA never locks bus access.
1 = USB packets HSB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of
fly-by HSB burst duration.
• BUFF_LENGTH: Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (64 KB)
is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer
end may occur earlier under USBA device control.
When this field is written, The DMASTATUSx register BUFF_COUNT field is updated with the write value.
Note:
Note:
32015G–AVR32–09/09
Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
For reliability it is highly recommended to wait for both DMASTATUSx register CHAN_ACT and CHAN_ENB flags are at 0, thus
ensuring the channel has been stopped before issuing a command other than “Stop Now”.
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