AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 17

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

7.2.1
32015G–AVR32–09/09
Pipeline Overview
Figure 7-1.
AVR32 AP is a pipelined processor with seven pipeline stages. The pipeline has three subpipes,
namely the Multiply pipe, the Execute pipe and the Data pipe. These pipelines may execute dif-
ferent instructions in parallel. Instructions are issued in order, but may complete out of order
(OOO) since the subpipes may be stalled individually, and certain operations may use a subpipe
for several clock cycles.
Figure 7-2 on page 18
Cache RAM interface
Tightly Coupled Bus
Overview of the AVR32 AP CPU
controller
shows an overview of the AVR32 AP pipeline stages.
Dcache
master
HSB
AVR32 CPU pipeline with Java accelerator
system
OCD
MMU
control
JTAG
control
controller
Reset
master
Icache
HSB
AT32AP7001
Cache RAM interface
BTB RAM interface
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