AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 782

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

37.4.5
37.5
Table 37-2.
32015G–AVR32–09/09
Instruction
OPCODE
0x0C
0x01
0x02
0x03
0x04
0x06
0x10
0x11
JTAG Instruction Summary
Memory programming
JTAG Instruction Summary
SAMPLE_PRELOAD
EXTEST
CLAMP
AVR_RESET
NEXUS_ACCESS
Instruction
IDCODE
INTEST
MEMORY_WORD_ACCESS
What to do if the error bit is set:
• During Shift-IR: The new instruction is selected. The last operation performed using the old
• During Shift-DR of an address: The previous operation failed. The new address is accepted. If
• During Shift-DR of read data: The read operation failed, and the read data are invalid.
• During Shift-DR of write data: The previous write operation failed. The new data are accepted
• While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not
The High-Speed Bus (HSB) in the device is mapped as a slave on the SAB. This enables all
HSB-mapped memories to be read or written through the SAB using JTAG instructions, as
described in
Internal SRAM can always be directly accessed. External static memory or SDRAM can be
accessed if the EBI has been correctly configured to access this memory. It is also possible to
access the configuration registers for these modules to set up the correct configuration. Simi-
larly, external parallel flash can be programmed by accessing the registers for the flash device
through the EBI.
Memory can be written while the CPU is executing, which can be utilized for debug purposes.
When downloading a new program, the AVR_RESET instruction should be used to freeze the
CPU, to prevent partially downloaded code from being executed.
The implemented JTAG instructions in the AVR32 are shown in the table below.
instruction did not complete successfully.
the read bit is set, a read operation is started.
and a write operation started. This should only occur during block writes or stream writes. No
error can occur between scanning a write address and the following write data.
have actually completed.
”Service Access Bus” on page
Description
Select the 32-bit Device Identification register as data register.
Take a snapshot of external pin values without affecting system
operation.
Select boundary scan chain as data register for testing circuitry
external to the device.
Select boundary scan chain for internal testing of the device.
Bypass device through Bypass register, while driving outputs from
boundary scan register.
Apply or remove a static reset to the device
Select the SAB Address and Data registers as data register for the
TAP. The registers are accessed in Nexus mode.
Select the SAB Address and Data registers as data register for the
TAP.
780.
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