AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 546

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

29.8.1
Register Name:
Access Type:
Offset:
Reset Value:
• MODE: Command Mode
32015G–AVR32–09/09
MODE
0
1
2
3
4
5
6
31
23
15
7
-
-
-
-
This field defines the command issued by the SDRAMC when the SDRAM device is accessed.
Mode Register
Description
Normal mode. Any access to the SDRAM is decoded normally.
The SDRAMC issues a “NOP” command when the SDRAM device is accessed regardless of the cycle.
The SDRAMC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of
the cycle.
The SDRAMC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the
cycle. This command will load the CR.CAS field into the SDRAM device Mode Register. All the other parameters
of the SDRAM device Mode Register will be set to zero (burst length, burst type, operating mode, write burst
mode...).
The SDRAMC issues an “Auto Refresh” command when the SDRAM device is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued.
The SDRAMC issues an “Extended Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. This command will load the LPR.PASR, LPR.DS, and LPR.TCR fields into the SDRAM
device Extended Mode Register. All the other bits of the SDRAM device Extended Mode Register will be set to
zero.
Deep power-down mode. Enters deep power-down mode.
30
22
14
6
-
-
-
-
MR
Read/Write
0x00
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
MODE
25
17
9
1
-
-
-
AT32AP7001
24
16
8
0
-
-
-
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