AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 505
AT32AP7001-ALUT
Manufacturer Part Number
AT32AP7001-ALUT
Description
IC MCU 32BIT AVR32 208-LQFP
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7001-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, POR, PWM, WDT
Number Of I /o
90
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, ISI, MCI, PS2, SPI, TWI, USB
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 1 Channel
Package
208PQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32AP7001-ALUT
Manufacturer:
EVERLIGHT
Quantity:
12 000
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32015G–AVR32–09/09
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
• if the write controlling signal has no hold time and the read controlling signal has no setup time
• in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the NCS
• in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing (NWEHOLD
Figure 28-18. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
(Figure 28-18 on page
signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode
28-19 on page
read wait state, the write operation could not complete properly.
= 0), the feedback of the write control signal is used to control address, data, chip select, and
byte select lines. If the external write control signal is not inactivated as expected due to load
capacitances, an early read wait state is inserted and address, data and control signals are
maintained one more cycle. See
NBS0, NBS1,
A0, A1
CLK_SMC
A[25:2]
D[15:0]
NWE
NRD
506). The write operation must end with a NCS rising edge. Without an early
505).
Write cycle
Figure 28-20 on page
No hold
Early Read
Wait state
507.
No setup
Read cycle
AT32AP7001
(Figure
505
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