AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 497
AT32AP7001-ALUT
Manufacturer Part Number
AT32AP7001-ALUT
Description
IC MCU 32BIT AVR32 208-LQFP
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7001-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, POR, PWM, WDT
Number Of I /o
90
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, ISI, MCI, PS2, SPI, TWI, USB
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 1 Channel
Package
208PQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32AP7001-ALUT
Manufacturer:
EVERLIGHT
Quantity:
12 000
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28.6.4.2
32015G–AVR32–09/09
Read mode
•Null Pulse
•Read is controlled by NRD (MODE.READMODE = 1)
Figure 28-10. No Setup, No Hold on NRD, and NCS Read Signals
Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads
to unpredictable behavior.
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
i n g s t o k n o w w h i c h s ig n a l r i s e s f i r s t . T h e R e a d M o d e b it i n t h e M O D E r e g i s t e r
(MODE.READMODE) of the corresponding chip select indicates which signal of NRD and NCS
controls the read operation.
Figure 28-11 on page 498
RAM. The read data is available t
ing edge of NRD. In this case, the MODE.READMODE bit must be written to one (read is
controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC sam-
ples the read data internally on the rising edge of CLK_SMC that generates the rising edge of
NRD, whatever the programmed waveform of NCS may be.
NBS0, NBS1,
A0, A1
CLK_SMC
A[25:2]
D[15:0]
NRD
NCS
NRDSETUP
NCSRDPULSE
NRDCYCLE
shows the waveforms of a read operation of a typical asynchronous
PACC
after the falling edge of NRD, and turns to ‘Z’ after the ris-
NRDPULSE
NCSRDPULSE
NRDCYCLE
NRDCYCLE
NRDPULSE
NCSRDPULSE
AT32AP7001
497
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