AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 96

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

11.5.3.2
11.5.3.3
11.5.4
32015G–AVR32–09/09
PLL0 clock
Osc0 clock
Synchronous clocks
Lock suppression
Operating range selection
PLLSEL
0
1
When using high division or multiplication factors, there is a possibility that the PLL can give
false lock indications while sweeping to the correct frequency. To prevent false lock indications
from setting the LOCKn flag, the lock indication can be suppressed for a number of slow clock
cycles indicated in the PLLn:COUNT field. Typical start-up times can be found using the Atmel
filter caluclator (see below).
To use PLLn, a passive RC filter should be connected to the LFTn pin, as shown in
Filter values depend on the PLL reference and output frequency range. Atmel provides a tool
named “Atmel PLL LFT Filter Calculator AT91”. The PLL for AT32AP7001 can be selected in
this tool by selecting “AT91RM9200 (58A07F)” and leave “Icp = ‘1’” (default).
Oscillator 0 (default) or PLL0 provides the source for the main clocks, which is the common root
for the synchronous clocks for the CPU, and HSB, PBA, and PBB modules. The main clock is
divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tap-
ping of this prescaler, or the undivided main clock, as long as f
The synchronous clock source can be changed on-the fly, responding to varying load in the
application. The clock domains can be shut down in sleep mode, as described in
on page
masked, to avoid power consumption in inactive modules.
Figure 11-3. Synchronous clock generation
Prescaler
99. Additionally, the clocks for each module in the four domains can be individually
CPUSEL
CPUDIV
0
1
Controller
Main clock
instruction
Sleep
Sleep
CPUMASK
Mask
CPU
f
HSB
AT32AP7001
CPU clocks
HSB clocks
PBB clocks
PBAclocks
f
PBx
”Sleep modes”
and f
Figure
PBB
=f
11-2.
HSB
96
.