DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 118
![IC H8S/2300 MCU FLASH 128QFP](/photos/12/29/122944/df2398f20v_sml.jpg)
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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DF2398F20V
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Figure 5-3 shows the timing of setting IRQnF.
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as
an I/O pin for another function.
5.3.2
There are 52 sources for internal interrupts from on-chip supporting modules.
5.3.3
Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the
lower the vector number, the higher the priority.
Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same
priority, and priorities within a module, are fixed as shown in table 5-4.
Rev.6.00 Oct.28.2004 page 88 of 1016
REJ09B0138-0600H
For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select
enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt
request is issued to the interrupt controller.
The interrupt priority level can be set by means of IPR.
The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. When the DMAC or DTC is activated
by an interrupt, the interrupt control mode and interrupt mask bits are not affected.
Internal Interrupts
Interrupt Exception Handling Vector Table
input pin
IRQnF
IRQn input
IRQn
Note: n=7 to 0
ø
Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0
IRQnSCA, IRQnSCB
detection circuit
Edge/level
Figure 5-3 Timing of Setting IRQnF
Clear signal
S
R
IRQnF
Q
IRQnE
IRQn interrupt
request
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