DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 139

IC H8S/2300 MCU FLASH 128QFP

DF2398F20V

Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398F20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.2.2
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access
space.
ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory
and internal I/O registers is fixed regardless of the settings in ASTCR.
ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or
in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to
be designated as a 2-state access space or a 3-state access space.
Wait state insertion is enabled or disabled at the same time.
Bit
Initial value :
R/W
Access State Control Register (ASTCR)
Bit n
ASTn
0
1
:
:
AST7
R/W
7
1
Description
Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
Area n is designated for 3-state access
Wait state insertion in area n external space is enabled
AST6
R/W
6
1
AST5
R/W
5
1
AST4
R/W
4
1
AST3
R/W
3
1
AST2
R/W
2
1
AST1
R/W
Rev.6.00 Oct.28.2004 page 109 of 1016
1
1
AST0
R/W
0
1
(Initial value)
REJ09B0138-0600H
(n = 7 to 0)

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