DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 189

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.10
6.10.1
The H8S/2357 Group can release the external bus in response to a bus request from an external device. In the external bus
released state, the internal bus master continues to operate as long as there is no external access.
If an internal bus master wants to make an external access in the external bus released state, or if a refresh request is
generated, it can issue a bus request off-chip.
6.10.2
In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving
the BREQ pin low issues an external bus request to the H8S/2357 Group. When the BREQ pin is sampled, at the
prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the
high-impedance state, establishing the external bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus
master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request
from the external bus master to be dropped. Even if a refresh request is generated in the external bus released state,
refresh control is deferred until the external bus master drops the bus request.
If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus
released state, or when a refresh request is generated, the BREQO pin is driven low and a request can be made off-chip to
drop the bus request.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released
state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is as follows:
If a refresh request and external bus release request occur simultaneously, the order of priority is as follows:
As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of
priority for these two operations.
Bus Release
Overview
Operation
(High) External bus release > Internal bus master external access (Low)
(High) Refresh > External bus release (Low)
Rev.6.00 Oct.28.2004 page 159 of 1016
REJ09B0138-0600H