DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 415

IC H8S/2300 MCU FLASH 128QFP

DF2398F20V

Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398F20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure.
Examples of PWM Mode Operation: Figure 10-25 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and
output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty.
TGRA
TGRB
H'0000
TIOCA
Select counter clearing source
Select waveform output level
Select counter clock
TCNT value
Set PWM mode
<PWM mode>
PWM mode
Start count
Set TGR
Figure 10-24 Example of PWM Mode Setting Procedure
Figure 10-25 Example of PWM Mode Operation (1)
[1]
[2]
[3]
[4]
[5]
[6]
Counter cleared by
TGRA compare match
[1] Select the counter clock with bits TPSC2 to
[2] Use bits CCLR2 to CCLR0 in TCR to select the
[3] Use TIOR to designate the TGR as an output
[4] Set the cycle in the TGR selected in [2], and set
[5] Select the PWM mode with bits MD3 to MD0 in
[6] Set the CST bit in TSTR to 1 to start the count
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
TGR to be used as the TCNT clearing source.
compare register, and select the initial value and
output value.
the duty in the other the TGR.
TMDR.
operation.
Rev.6.00 Oct.28.2004 page 385 of 1016
Time
REJ09B0138-0600H

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