DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 692

IC H8S/2300 MCU FLASH 128QFP

DF2398F20V

Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398F20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20.2
20.2.1
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Note: * R/W in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Reserved: In the H8S/2357 and H8S/2352, this bit cannot be modified and is always read as 0. Only 0 should be
written. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Only 0 should be written to this bit.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master.
Rev.6.00 Oct.28.2004 page 662 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Register Descriptions
System Clock Control Register (SCKCR)
Bit 2
SCK2
0
1
Bit 7
PSTOP
0
1
:
:
PSTOP
R/W
7
0
Bit 1
SCK1
0
1
0
1
Normal Operation
ø output (initial value)
Fixed high
R/W
6
0
Bit 0
SCK0
0
1
0
1
0
1
—/(R/W)*
5
0
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
Sleep Mode
ø output
Fixed high
4
0
Description
3
0
Software
Standby Mode
Fixed high
Fixed high
SCK2
R/W
2
0
SCK1
R/W
1
0
Hardware
Standby Mode
High impedance
High impedance
SCK0
R/W
0
0
(Initial value)

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