DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 52

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.1.2
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
There are also differences in the address space, CCR and EXR functions, power-down state, etc., depending on the
product.
2.1.3
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
Rev.6.00 Oct.28.2004 page 22 of 1016
REJ09B0138-0600H
Power-down state
Register configuration
The MAC register is supported only by the H8S/2600 CPU.
Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU.
Number of execution states
The number of exection states of the MULXU and MULXS instructions.
More general registers and control registers
Expanded address space
Enhanced addressing
Enhanced instructions
Higher speed
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Eight 16-bit expanded registers, and one 8-bit control register, have been added.
Advanced mode supports a maximum 16-Mbyte address space.
The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
2-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
Basic instructions execute twice as fast.
Differences between H8S/2600 CPU and H8S/2000 CPU
Differences from H8/300 CPU
Instruction
MULXU
MULXS
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
H8S/2600
3
4
4
5
Internal Operation
H8S/2000
12
20
13
21