DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 267

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.7
DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting
state) channel setting should not be changed. The operating channel setting should only be changed when transfer is
disabled.
Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(a) DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is
Figure 7-40 shows an example of the update timing for DMAC registers in dual address transfer mode.
updated in the bus cycle before DMAC transfer.
Usage Notes
DMA Internal
address
DMA register
operation
DMA control
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Notes: 1. In single address transfer mode, the update timing is the same as [1].
ø
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
Block transfer counter ETCR operation (decremented, in last transfer cycle of a block
in block transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
2. The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Idle
[1]
Figure 7-40 Example of DMAC Register Update Timing
Transfer
source
Read
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
[1]
Transfer
source
Read
[2']
DMA read
Rev.6.00 Oct.28.2004 page 237 of 1016
DMA last transfer cycle
destination
Transfer
Write
DMA write
[3]
Dead
DMA
dead
REJ09B0138-0600H
Idle