DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 488

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT
overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by
overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during
watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2357 Group if TCNT
overflows during watchdog timer operation.
Bit 6
RSTE
0
1
Note: * The modules within the H8S/2357 Group are not reset, but TCNT and TCSR within the WDT are reset.
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer
operation.
For details of the types of resets, see section 4, Exception Handling.
Bit 5
RSTS
0
1
Note: * Manual reset is supported only in the H8S/2357 ZTAT. In the models except the H8S/2357 ZTAT, only 0 should be
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
Rev.6.00 Oct.28.2004 page 458 of 1016
REJ09B0138-0600H
written to this bit.
on Register Access.
Description
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Description
Reset signal is not generated if TCNT overflows*
Reset signal is generated if TCNT overflows
Description
Power-on reset
Manual reset*
(Initial value)
(Initial value)
(Initial value)