DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 218

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1.
Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0.
Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected
by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to
the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and
issues a transfer end interrupt request to the CPU.
The conditions for the DTE bit being cleared to 0 are as follows:
When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source
selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed.
The condition for the DTE bit being set to 1 is as follows:
Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1.
Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0.
Rev.6.00 Oct.28.2004 page 188 of 1016
REJ09B0138-0600H
When initialization is performed
When the specified number of transfers have been completed
When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason
When 1 is written to the DTE bit after the DTE bit is read as 0
Bit 7
DTME1
0
1
Bit 5
DTME0
0
1
Bit 6
DTE1
0
1
Bit 4
DTE0
0
1
Description
Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt
Data transfer enabled
Description
Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value)
Data transfer enabled
Description
Data transfer disabled
Data transfer enabled
Description
Data transfer disabled
Data transfer enabled
(Initial value)
(Initial value)
(Initial value)