DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 191

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.10.4
Figure 6-37 shows the timing for transition to the bus-released state.
6.10.5
When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts.
Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep
mode.
Transition Timing
Usage Note
Address bus
HWR, LWR
BREQO *
[1]
[2]
[3]
[4]
[5]
[6]
Note: * Output only when BREQOE is set to 1.
Data bus
BREQ
BACK
RD
AS
ø
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
BREQO signal goes high 1.5 clocks after BACK signal goes high.
T
0
Figure 6-37 Bus-Released State Transition Timing
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
[2]
External bus released state
[3]
2
state.
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
Rev.6.00 Oct.28.2004 page 161 of 1016
[5]
cycle
CPU
[6]
REJ09B0138-0600H