DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 551

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.2.2
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2,
TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR).
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back
from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode.
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state.
Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR).
However, the setting conditions for the TEND bit, are as shown below.
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Bit
Initial value :
R/W
Serial Status Register (SSR)
Bit 4
ERS
0
1
Bit 2
TEND
0
1
:
:
R/(W)*
TDRE
7
1
Description
[Clearing conditions]
[Setting condition]
When the low level of the error signal is sampled
Description
[Clearing conditions]
[Setting conditions]
Upon reset, and in standby mode or module stop mode
When 0 is written to ERS after reading ERS = 1
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
Upon reset, and in standby mode or module stop mode
When the TE bit in SCR is 0 and the ERS bit is also 0
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a
1-byte serial character when GM = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
R/(W)*
ERS
4
0
R/(W)*
PER
3
0
TEND
2
1
R
MPB
Rev.6.00 Oct.28.2004 page 521 of 1016
1
0
R
MPBT
R/W
0
0
(Initial value)
(Initial value)
REJ09B0138-0600H