DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 250
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2398F20V
Manufacturer:
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Full Address Mode (Burst Mode): Figure 7-21 shows a transfer example in which TEND output is enabled and word-
size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-
state access space.
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the
burst transfer ends.
If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is
cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the
DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is
suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues
to the end of the transfer even if the DTME bit is cleared.
Rev.6.00 Oct.28.2004 page 220 of 1016
REJ09B0138-0600H
Address bus
TEND
HWR
Bus release
LWR
RD
ø
Figure 7-21 Example of Full Address Mode (Burst Mode) Transfer
DMA
read
DMA
write
DMA
read
Burst transfer
DMA
write
DMA
read
Last transfer cycle
DMA
write
DMA
dead
Bus release
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