DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 363

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Port G Data Direction Register (PGDDR)
Modes 6, 7
Modes 4, 5
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR
cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read.
The PG4DDR bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes 4 and 5, and to 0 in
modes 6 and 7. It retains its prior state after a manual reset* and in software standby mode. The OPE bit in SBYCR is
used to select whether the bus control output pins retain their output state or become high-impedance when a transition is
made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a
manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bit
Initial value :
R/W
Initial value :
R/W
Bit
Initial value :
R/W
Mode 7*
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing the bit to 0 makes the pin
an input port.
Modes 4 to 6*
Pins PG
and as input ports when the bits are cleared to 0.
Pin PG
PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. For details of the
DRAM interfaces, see section 6, Bus Controller.
0
4
functions as the CAS output pin when DRAM interface is designated. Otherwise, setting the corresponding
to PG
:
:
:
:
:
Undefined Undefined Undefined
Undefined Undefined Undefined
Undefined Undefined Undefined
1
—
—
—
—
—
function as bus control output pins (CS0 to CS3) when the corresponding PGDDR bits are set to 1,
7
7
—
—
—
—
—
6
6
—
—
—
—
—
5
5
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
PG4DR
R/W
W
W
0
1
0
4
4
PG3DR
R/W
W
W
3
0
0
3
0
PG2DR
R/W
W
W
2
0
0
2
0
PG1DR
R/W
W
W
Rev.6.00 Oct.28.2004 page 333 of 1016
1
0
0
1
0
4
PG0DR
to PG
R/W
W
W
0
0
0
0
0
0
).
REJ09B0138-0600H