AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 115

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4338F–USB–08/07
Table 88. SSCS (094h) Read - Synchronous Serial Control and Status Register
Table 89. SSADR (096h) - Synchronous Serial Address Register (read/write)
Number
Number
Number
SC4
Bit
Bit
Bit
A7
1
0
7
0
1
2
3
4
5
6
7
7
7
6
5
4
3
2
1
0
Mnemonic Description
Mnemonic Description
Mnemonic Description
SD1
SD0
SC3
SC0
SC1
SC2
SC3
SC4
Bit
Bit
Bit
GC
A6
A7
A6
A5
A4
A3
A2
A1
6
0
0
0
6
Address bit 1 or Data bit 1.
Address bit 0 (R/W) or Data bit 0.
Always zero
Always zero
Always zero
Status Code bit 0
See Table 81 to Table 85
Status Code bit 1
See Table 81 to Table 85
Status Code bit 2
See Table 81 to Table 85
Status Code bit 3
See Table 81 to Table 85
Status Code bit 4
See Table 81 to Table 85
Slave address bit 7.
Slave address bit 6.
Slave address bit 5.
Slave address bit 4.
Slave address bit 3.
Slave address bit 2.
Slave address bit 1.
General call bit
Clear to disable the general call address recognition.
Set to enable the general call address recognition.
SC2
A5
5
5
SC1
A4
4
4
SC0
A3
3
3
A2
2
0
2
A1
1
0
1
A0
0
0
0
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