AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 138

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

138
AT89C5131A-L
Table 94. USBIEN Register
USBIEN (S:BEh)
USB Global Interrupt Enable Register
Reset Value = 10h
Table 95. USBADDR Register
USBADDR (S:C6h)
USB Address Register
Reset Value = 80h
Bit Number
Bit Number Bit Mnemonic Description
FEN
6-0
7-6
7
7
-
7
5
4
3
2
1
0
Mnemonic Description
UADD[6:0]
UADD6
EWUPCPU
EEOFINT
ESOFINT
ESPINT
FEN
Bit
6
6
-
-
-
-
Function Enable
Set this bit to enable the address filtering function.
Cleared this bit to disable the function.
USB Address
This field contains the default address (0) after power-up or USB bus reset.
It will be written with the value set by a SET_ADDRESS request received by the
device firmware.
EWUPCPU
UADD5
Reserved
The value read from these bits is always 0. Do not set these bits.
Enable Wake Up CPU Interrupt
Set this bit to enable Wake Up CPU Interrupt. (See “USBIEN Register
USBIEN (S:BEh) USB Global Interrupt Enable Register” on page 138.)
Clear this bit to disable Wake Up CPU Interrupt.
Enable End Of Reset Interrupt
Set this bit to enable End Of Reset Interrupt. (See “USBIEN Register USBIEN
(S:BEh) USB Global Interrupt Enable Register” on page 138.). This bit is set
after reset.
Clear this bit to disable End Of Reset Interrupt.
Enable SOF Interrupt
Set this bit to enable SOF Interrupt. (See “USBIEN Register USBIEN (S:BEh)
USB Global Interrupt Enable Register” on page 138.).
Clear this bit to disable SOF Interrupt.
Reserved
The value read from these bits is always 0. Do not set these bits.
Enable Suspend Interrupt
Set this bit to enable Suspend Interrupts (see the “USBIEN Register USBIEN
(S:BEh) USB Global Interrupt Enable Register” on page 138).
Clear this bit to disable Suspend Interrupts.
5
5
EEORINT
UADD4
4
4
ESOFINT
UADD3
3
3
UADD2
2
2
-
UADD1
1
1
-
4338F–USB–08/07
ESPINT
UADD0
0
0