AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 69

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Baud Rate Selection for
UART for Mode 1 and 3
Baud Rate Selection Table for
UART
Internal Baud Rate Generator
(BRG)
4338F–USB–08/07
SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit addressable
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 37. Baud Rate Selection
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
(T2CON)
7
TCLK
TIMER1
X
X
X
TIMER2
TIMER1
TIMER2
0
1
0
1
0
1
INT_BRG
INT_BRG
6
(T2CON)
RCLK
0
0
1
1
0
1
X
X
X
RCLK
TCLK
0
1
0
1
5
(BDRCON)
TBCK
TIMER_BRG_RX
TIMER_BRG_TX
0
0
0
0
1
1
0
0
1
4
(BDRCON)
RBCK
3
0
0
0
0
0
0
1
1
1
RBCK
TBCK
0
1
0
1
2
Clock Source
UART Tx
INT_BRG
INT_BRG
INT_BRG
Timer 1
Timer 2
Timer 1
Timer 2
Timer 1
Timer 2
/ 16
/ 16
1
Rx Clock
Tx Clock
Clock Source
UART Rx
INT_BRG
INT_BRG
INT_BRG
Timer 1
Timer 1
Timer 2
Timer 2
Timer 1
Timer 2
0
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