AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 147

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4338F–USB–08/07
Table 105. UFNUMH Register
UFNUMH (S:BBh, read-only)
USB Frame Number High Register
Reset Value = 00h
Table 106. UFNUML Register
UFNUML (S:BAh, read-only)
USB Frame Number Low Register
Reset Value = 00h
Bit Number
Number
FNUM7
Bit
2-0
7 - 0
5
4
3
7
7
-
Mnemonic
FNUM[10:8]
Mnemonic Description
CRCERR
FNUM[7:0]
CRCOK
FNUM6
Bit
Bit
-
6
6
-
Description
Frame Number CRC OK
This bit is set by hardware when a new Frame Number in Start of Frame Packet
is received without CRC error.
This bit is updated after every Start of Frame packet receipt.
Important note: the Start of Frame interrupt is generated just after the PID receipt.
Frame Number CRC Error
This bit is set by hardware when a corrupted Frame Number in Start of Frame
packet is received.
This bit is updated after every Start of Frame packet receipt.
Important note: the Start of Frame interrupt is generated just after the PID receipt.
Reserved
The value read from this bit is always 0. Do not set this bit.
Frame Number
FNUM[10:8] are the upper 3 bits of the 11-bit Frame Number (see the “UFNUML
Register UFNUML (S:BAh, read-only) USB Frame Number Low Register” on
page 147). It is provided in the last received SOF packet (see SOFINT in the
“USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register” on
page 138). FNUM is updated if a corrupted SOF is received.
Frame Number
FNUM[7:0] are the lower 8 bits of the 11-bit Frame Number (See “UFNUMH
Register UFNUMH (S:BBh, read-only) USB Frame Number High Register” on
page 147.).
CRCOK
FNUM5
5
5
CRCERR
FNUM4
4
4
FNUM3
3
3
-
FNUM10
FNUM2
2
2
FNUM9
FNUM1
1
1
FNUM8
FNUM0
0
0
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