AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 29

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 16. Flash Memory Architecture
FM0 Memory Architecture
User Space
Extra Row (XRow)
Hardware Security Space
Column Latches
Overview of FM0
Operations
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
4338F–USB–08/07
Column Latches (128 Bytes)
Hardware Security (1 Byte)
Extra Row (128 Bytes)
The Flash memory is made up of 4 blocks (see Figure 16):
1. The memory array (user space) 32 Kbytes
2. The Extra Row
3. The Hardware security bits
4. The column latch registers
This space is composed of a 32 Kbytes Flash memory organized in 256 pages of 128
bytes. It contains the user’s application code.
This row is a part of FM0 and has a size of 128 bytes. The extra row contains informa-
tion for bootloader usage. (see Table 39.Software Registers, page 39)
The hardware security space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software. The 4 LSB can only be read by software
and written by hardware in parallel mode.
The column latches, also part of FM0, have a size of full page (128 bytes).
The column latches are the entrance buffers of the three previous memory locations
(user array, XRow and Hardware security byte).
The CPU interfaces to the Flash memory through the FCON register and AUXR1
register.
These registers are used to:
•
•
•
•
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting this bit takes precedence on the EXTRAM bit in AUXR register.
7FFFh
0000h
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the Flash memory (busy/not busy)
Select the Flash memory FM0/FM1.
Flash Memory
32 Kbytes
User Space
FM0
FFFFh
F400h
FM1 mapped between FFFFh and
F400h when bit ENBOOT is set in
AUXR1 register
Flash Memory
Boot Space
3 Kbytes
FM1
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