AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 140

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

140
AT89C5131A-L
Table 97. UEPCONX Register
UEPCONX (S:D4h)
USB Endpoint X Control Register
Note:
Reset Value = 80h when UEPNUM = 0 (default Control Endpoint)
Reset Value = 00h otherwise for all other endpoints
Bit Number
EPEN
1-0
7
7
6
5
4
3
2
1. (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)
EPTYPE[1:0]
Mnemonic
EPDIR
EPEN
DTGL
6
-
Bit
-
-
-
Description
Endpoint Enable
Set this bit to enable the endpoint according to the device configuration.
Endpoint 0 will always be enabled after a hardware or USB bus reset and
participate in the device configuration.
Clear this bit to disable the endpoint according to the device configuration.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is always 0. Do not set this bit.
Data Toggle (Read-only)
This bit is set by hardware when a valid DATA0 packet is received and
accepted.
This bit is cleared by hardware when a valid DATA1 packet is received and
accepted.
Endpoint Direction
Set this bit to configure IN direction for Bulk, Interrupt and Isochronous
endpoints.
Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous
endpoints.
This bit has no effect for Control endpoints.
Endpoint Type
Set this field according to the endpoint configuration (Endpoint 0 will always be
configured as control):
00Control endpoint
01Isochronous endpoint
10Bulk endpoint
11Interrupt endpoint
5
-
4
-
DTGL
3
EPDIR
2
EPTYPE1
1
4338F–USB–08/07
EPTYPE0
0