AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 15

MCU 8051 32K FLASH USB 52-PLCC

AT89C5131A-S3SUL

Manufacturer Part Number
AT89C5131A-S3SUL
Description
MCU 8051 32K FLASH USB 52-PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheets

Specifications of AT89C5131A-S3SUL

Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
2-Wire, EUART, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
34
Number Of Timers
3 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89STK-05
Minimum Operating Temperature
- 40 C
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C5131A-S3SUL
Manufacturer:
Atmel
Quantity:
10 000
PLL Programming
Divider Values
4338F–USB–08/07
The PLL is programmed using the flow shown in Figure 11. As soon as clock generation
is enabled user must wait until the lock indicator is set to ensure the clock output is
stable.
Figure 11. PLL Programming Flow
To generate a 48 MHz clock using the PLL, the divider values have to be configured fol-
lowing the oscillator frequency. The typical divider values are shown in Table 13.
Table 13. Typical Divider Values
Oscillator Frequency
12 MHz
16 MHz
18 MHz
20 MHz
24 MHz
32 MHz
40 MHz
3 MHz
6 MHz
8 MHz
R+1
Configure Dividers
16
12
12
Programming
8
6
4
3
8
2
3
PLL Locked?
N3:0 = xxxxb
R3:0 = xxxxb
LOCK = 1?
Enable PLL
PLLEN = 1
PLL
N+1
10
1
1
1
1
1
3
5
1
2
PLLDIV
F0h
B4h
B9h
70h
50h
30h
20h
72h
10h
21h
15

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