AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 14

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PLL
PLL Description
Figure 9. PLL Block Diagram and Symbol
14
AT89C5131A-L
CLOCK
OSC
N divider
N3:0
Figure 8. Crystal Connection
The AT89C5131A-L PLL is used to generate internal high frequency clock (the USB
Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL
clock is used to generate the USB interface clock. Figure 9 shows the internal structure
of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Figure 9) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Figure 10). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 10. PLL Filter Connection
The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.
PLLCON.1
PLLCON.0
PLOCK
PLLEN
USBclk
PFLD
Down
=
Up
OSCclk
---------------------------------------------- -
R divider
R3:0
PLLF
CHP
PLLF
N
VSS
+
×
1
(
R
+
Vref
C1
C2
1
)
VSS
R
VCO
C1
Q
VSS
X1
X2
C2
USB Clock Symbol
USB Clock
CLOCK
USB
4338F–USB–08/07
REF
pro-