AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 30

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Launching Programming
Status of the Flash Memory
Selecting FM0/FM1
30
AT89C5131A-L
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 34. A MOVC instruction is then used for reading these spaces.
Table 34. FM0 Blocks Select Bits
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5 followed by A. Table 35 summarizes the memory
spaces to program according to FMOD1:0 bits.
Table 35. Programming Spaces
The Flash memory enters a busy state as soon as programming is launched. In this
state, the memory is not available for fetching code. Thus to avoid any erratic execution
during programming, the CPU enters Idle mode. Exit is automatically performed at the
end of programming.
Note:
The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped
up to F800h.
Extra Row
Reserved
Security
Space
User
FMOD1
Interrupts that may occur during programming time must be disabled to avoid any spuri-
ous exit of the idle mode.
0
0
1
1
FPL3:0
A
A
A
A
5
5
5
5
FMOD0
FPS
0
1
0
1
Write to FCON
X
X
X
X
X
X
X
X
FMOD1
FM0 Adressable Space
User (0000h-FFFFh)
Extra Row(FF80h-FFFFh)
Hardware Security (0000h)
reserved
0
0
0
0
1
1
1
1
FMOD0
0
0
1
1
0
0
1
1
Operation
No action
Write the column latches in user
space
No action
Write the column latches in extra row
space
No action
Write the fuse bits space
No action
No action
4338F–USB–08/07