HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 117

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Legend:
I:
O:
I/O:
Power: Power supply
Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in
Pin
No.
TDO
TCK
VDD-CPG
VSS-CPG
Pin Name
VDD
VSS
TMS
TDI
TRST
VDD-PLL2
VSS-PLL2
VDD-PLL1
VSS-PLL1
XTAL
EXTAL
hardware standby mode.
Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the
on-chip PLL circuits are used.
Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-
chip crystal oscillation circuit is used.
Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-
chip RTC is used.
VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package.
The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP package.
For a QFP package, the maximum operating frequency of the external bus is 84 MHz.
*
Input
Output
Input/output
Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.
O
Power
Power
I
I
I
I
Power
Power
Power
Power
Power
Power
O
I
I/O
Function
Data out
(H-UDI)
Internal VDD
Internal GND
(0 V)
Mode (H-UDI)
Clock (H-UDI)
Data in (H-UDI)
Reset (H-UDI)
PLL2 VDD (3.3V)
PLL2 GND (0V)
PLL1 VDD (3.3V)
PLL1 GND (0V)
CPG VDD (3.3V)
CPG GND (0V)
Crystal resonator
External input
clock/crystal
resonator
Reset
SRAM
Rev.7.00 Oct. 10, 2008 Page 31 of 1074
DRAM
Memory Interface
SDRAM PCMCIA MPX
Section 1 Overview
REJ09B0366-0700